TXDSTALL=0, SAEN=0, GCEN=0, ACKSTALL=0, ADRSTALL=0, TXCFG=0, HSMEN=0, RXCFG=0, RXSTALL=0, IGNACK=0, ADDRCFG=000
Slave Configuration Register 1
| ADRSTALL | Address SCL Stall 0 (0): Clock stretching disabled. 1 (1): Clock stretching enabled. |
| RXSTALL | RX SCL Stall 0 (0): Clock stretching disabled. 1 (1): Clock stretching enabled. |
| TXDSTALL | TX Data SCL Stall 0 (0): Clock stretching disabled. 1 (1): Clock stretching enabled. |
| ACKSTALL | ACK SCL Stall 0 (0): Clock stretching disabled. 1 (1): Clock stretching enabled. |
| GCEN | General Call Enable 0 (0): General Call address is disabled. 1 (1): General call address is enabled. |
| SAEN | SMBus Alert Enable 0 (0): Disables match on SMBus Alert. 1 (1): Enables match on SMBus Alert. |
| TXCFG | Transmit Flag Configuration 0 (0): Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. 1 (1): Transmit Data Flag will assert whenever the transmit data register is empty. |
| RXCFG | Receive Data Configuration 0 (0): Reading the receive data register will return receive data and clear the receive data flag. 1 (1): Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag. |
| IGNACK | Ignore NACK 0 (0): Slave will end transfer when NACK detected. 1 (1): Slave will not end transfer when NACK detected. |
| HSMEN | High Speed Mode Enable 0 (0): Disables detection of Hs-mode master code. 1 (1): Enables detection of Hs-mode master code. |
| ADDRCFG | Address Configuration 0 (000): Address match 0 (7-bit). 1 (001): Address match 0 (10-bit). 2 (010): Address match 0 (7-bit) or Address match 1 (7-bit). 3 (011): Address match 0 (10-bit) or Address match 1 (10-bit). 4 (100): Address match 0 (7-bit) or Address match 1 (10-bit). 5 (101): Address match 0 (10-bit) or Address match 1 (7-bit). 6 (110): From Address match 0 (7-bit) to Address match 1 (7-bit). 7 (111): From Address match 0 (10-bit) to Address match 1 (10-bit). |